The present disclosure relates to semiconductor memory devices including an error checking and correcting (ECC) circuit.
In recent years, there has been a demand for embedded dynamic random access memory (DRAM) devices having higher integration density in order to achieve a low-cost system on chip (SOC). Most of the memory area is occupied by the memory array portion. In order to achieve a higher integration density, the area of a memory cell itself has been reduced by applying microfabrication technology to memory cell transistors, or memory capacitors including high-k insulating film.
In the case of a stacked memory cell, although the capacitor surface area decreases with decreasing memory cell area, a desired capacitor capacity is ensured by introducing an additional high-k insulating film. However, in order to increase the capacitor capacitance, the insulating film needs to be thinned to an extremely small thickness, resulting in an increase in tunnel leakage current in the capacitor insulating film. Moreover, because logic compatibility is strongly required in the microfabrication process, storage nodes are silicided. However, this causes an increase in junction leakage at the storage node. Therefore, the charge retention time of the cell disadvantageously decreases. It is also necessary to address a degradation in reliability of the charge retention time, the cell access time, etc. which is caused by changes over time of the characteristics of a cell capacitor or a transistor after manufacture. It is known that the ECC technique is useful for reducing or preventing the degradation in charge retention characteristics and reliability of a cell.
United States Patent Publication No. 2006/0112321 (Patent Document 1) describes a semiconductor memory device including an ECC circuit. In particular, this document describes a sequence technique for performing error correction operation having a byte write function. Specifically, word lines and sense amplifiers are continuously activated in a series of sequences in which error-corrected read data, replacement data obtained by replacing a portion of the data with external data, and parity data generated from the replacement data, are written back to memory cells.
Japanese Patent Publication No. 2003-59290 (Patent Document 2) describes a configuration for performing error correction operation having a byte write function. Specifically, a portion (m bits) of n-bit error correction read data is replaced with external input data, and the resulting data is written back, where n and m are natural numbers which satisfy n>m.
Japanese Patent Publication No. 2005-25827 (Patent Document 3) describes a synchronous DRAM (SDRAM) device in which read/modify/write operation is performed in order to achieve ECC operation having a byte mask function. Specifically, syndrome generation and error correction are completed during read latency. When write operation is performed, error-corrected read data is previously prepared during read latency, and parity generation and write back operation are executed during each burst cycle after the read latency has elapsed, whereby burst data input can be interrupted.
Japanese Patent Publication No. 2006-244632 (Patent Document 4) describes an SDRAM device in which pipeline read/modify/write operation is performed in order to achieve ECC operation having a byte mask function. In order to reduce or prevent bus collision during read operation preceding write operation and during write back operation of write data and parity data, DQ lines for read operation and DQ lines for write operation are separately provided, or read operation and write operation are separately performed during even-numbered and odd-numbered cycles of burst operation.
When stored data is read in these semiconductor memory devices, initially, signals of a plurality of bits corresponding to a row address are read from the memory cell array, and are amplified and held by sense amplifiers (row address strobe (RAS) cycle). Thereafter, at column gates, signals of a portion of the plurality of bits selected based on a column address are input via a buffer to an ECC circuit and are subjected to error checking and correcting, and the resulting data is output as read data from the semiconductor memory device (column address strobe (CAS) cycle).
Japanese Patent Publication No. 2009-93704 (Patent Document 5) describes a technique of reducing a CAS access time during random and page operations in an embedded DRAM device having a byte mask function. Specifically, during a RAS access time period, memory cell data is transferred, amplified, and held in a read amplifier, and during page write operation, write data is simultaneously written to a memory cell and a read amplifier which also serves as a data latch.
U.S. Pat. No. 7,051,264 (Patent Document 6) describes a technique of increasing a clock cycle rate. Specifically, in a semiconductor memory device in which write data latency is required, but one random cycle ECC operation is completed during one clock, write operation is performed in a two-stage pipeline process including the first stage in which parity generation and latching in a register are performed and the second stage in which data is written back to a memory cell.
However, in the techniques of Patent Documents 1-4, when a portion of signals of a plurality of bits read from the memory cell array are selected based on a column address, the selection and the error checking and correcting, etc. are performed after the column address is settled. Therefore, it is difficult to reduce the CAS access time, and therefore, it is difficult to increase the memory access rate.
The technique described in Patent Document 5 has been made in view of the above problems to provide a memory device with an ECC function in which the CAS access time is reduced, whereby the data transfer efficiency can be easily increased. However, in order to achieve a write mask function, it is necessary to perform error correction, parity generation, and write back operation to a memory cell during the same cycle when write operation is performed. Therefore, it is disadvantageously difficult to reduce the CAS cycle time.
In the technique described in Patent Document 6, it is necessary to perform one random cycle operation of word line activation, sense amplifier amplification and column access, word line inactivation, and precharge operation during at least one clock. Therefore, it is difficult to increase the clock cycle and thereby increase the data bandwidth, and in addition, the power consumption increases. Also, a byte write function is not provided, and therefore, it is disadvantageously difficult to increase the efficiency of use of a bus, particularly in a memory device having a multibus width, such as embedded DRAM devices.